1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method of forming layers of sidewall spacers upon a gate conductor to produce a graded junction which minimizes hot-carrier effects.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor ("MOS") transistor is well-known. Fabrication begins by lightly doping a single crystal silicon substrate n-type or p-type. The specific area where the transistor will be formed is then isolated from other areas on the substrate using various isolation structures. In modem fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with dielectric oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon ("LOCOS") structures. A gate dielectric is then formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal ("RTA") apparatus. A gate conductor is then patterned from a layer of polycrystalline silicon ("polysilicon") deposited upon the gate dielectric. The polysilicon is rendered conductive by doping it with ions from an implanter or a diffusion furnace. The gate conductor is patterned using a mask followed by exposure, development, and etching. Subsequently, source and drain regions are doped, via ion implantation, with a high dosage n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
FIG. 1 shows a top view of such a transistor. The transistor is formed in active region 26 of semiconductor substrate 10, between isolation areas 18 and 20. Isolation areas 18 and 20 preferably comprise shallow trench isolation structures filled with a dielectric oxide. A polysilicon layer is deposited upon the semiconductor topography and then patterned to form gate conductor 22. N-type or p-type species are implanted into the semiconductor substrate to form source region 26, drain region 28, and to render the polysilicon layer conductive. An interlevel dielectric is then deposited upon the semiconductor topography (not shown) to electrically isolate the underlying transistor from the overlying metal layers. Contact holes are etched into the interlevel dielectric and then metal is deposited into the holes to establish electrical contacts. Structures 42, 44, and 46 are such electrical contacts. Electrical contact 42 is described in more detail in subsequent cross-sectional views along plane A.
FIG. 2 is a partial cross-sectional view along plane A of semiconductor substrate 10. Isolation structure 18 is shown as a shallow trench isolation structure. Gate conductor 22 is shown terminating over and above isolation structure 18. Conformal oxide layer 30 is then deposited upon the semiconductor topography preferably using a CVD process. Oxide layer 30 is then etched using an anisotropic plasma etch. An anisotropic etch removes the oxide from substantially horizontal surfaces faster than oxide from substantially vertical surfaces. The anisotropic etch thereby leaves spacers 32 and 34 on the vertical sidewall surfaces of gate conductor 22. Spacer structures 32 and 34 are typically formed for two reasons: (i) to be used in forming a lightly doped drain ("LDD") structure, and (ii) to be used in aligning silicide areas on the source, drain, and gate conductor.
FIG. 3 is a processing step subsequent to FIG. 2 in which an interlevel dielectric 36 is deposited across the semiconductor topography. Interlevel dielectric 36 is deposited to electrically isolate the underlying gate conductors and source and drain regions from the subsequently formed, overlying metal interconnect. Interlevel dielectric 36 typically comprises glass deposited using a spin-on process or chemical vapor deposition. Boron and phosphorus may be incorporated into the glass during the deposition to reduce stress in the glass, improve step coverage, and to enable the dielectric to flow at lower temperatures. After initial deposition, the upper surface of interlevel dielectric 36 follows the contour of the underlying structure. The wafer is then heated, typically at a temperature of approximately 800.degree. C., and interlevel dielectric 36 flows to fill in existing gaps and produce a more planar upper surface.
FIG. 4 is a processing step subsequent to FIG. 3 in which a photoresist layer is deposited upon interlevel dielectric 36 and then patterned to expose portion 38 of the upper surface of interlevel dielectric 36. A hole is subsequently etched through interlevel dielectric 36. An anisotropic etch is typically used which combines physical and chemical etching. This produces a hole with substantially vertical sidewalls. The chemical part of the etch is selected so as to be selective to oxide. Since spacer 34 comprises silicon dioxide, it is also attacked by the etchant and may also be removed during the etch process. In that case, the etchant will reach the trench dielectric fill which also typically comprises some form of oxide. As a result, since all these materials have very similar responsiveness to the etch, the etch may go completely through the isolation material fl 8 to silicon substrate 10. Etches are usually stopped by the presence of a material with dissimilar etch characteristics. When such a material is detected, a signal is sent and the etch stops. In this case, since all the materials present have similar etch characteristics, it is difficult at best to determine etch end point. The result shown in FIG. 4 indicates removal of an oxide spacer; however, a spacer of dissimilar material (i.e., nitride or polysilicon) would not be removed.
FIG. 5 is a processing step subsequent to FIG. 4 in which a metal 44 is deposited into contact 42 opening for the establishment of an electrical connection. Metals like aluminum or tungsten are typically used. Chemical-mechanical polishing ("CMP") is applied to the wafer to remove any metal exterior to the hole and planarize the top surface. After the CMP, upper surface of metal 44 is at the same vertical level as upper surface of interlevel dielectric 36. Metal 44 is deposited to electrically connect the gate conductor to the source and both of them to an overlying metal interconnect line. The gate conductor is shorted to the source so that the transistor emulates a diode. If the previous etch has attacked the trench dielectric so that a hole exists into the underlying silicon, an undesirable electrical short will also be established between semiconductor substrate 10, gate conductor 22 and the source of the transistor. It would therefore be desirable to prevent the etchant from attacking the underlying trench dielectric. This will prevent metal from being deposited upon the exposed substrate silicon and establishing an electrical short.
Spacers 32 and 34 serve to reduce the maximum electric field E.sub.m which exists near the drain side of the channel area. Although not shown in FIGS. 2-5, the channel area exists along plane B of FIG. 1. The spacers occur not only in the active regions but also on all sidewall surfaces associated with the gate conductors. Absent spacers, an inversion-layer charges (or carriers) are accelerated into the overlying gate oxide. The carriers become trapped in the gate dielectric, a phenomenon generally called the hot-carrier effect. The injection of hot carriers into the gate dielectric damages the substrate/gate dielectric interface. Over time, operational characteristics of the device may degrade due to this damage, that degradation resulting in, e.g., improper variation of threshold voltage, linear region transconductance, subthreshold slope, and saturation current. This may eventually reduce the lifetime of the devices. Spacers 32 and 34 reduce E.sub.m by minimizing the abruptness in voltage changes near the drain side of the channel. Disbursing abrupt voltage changes reduces Em strength and the harmful hot-carrier effects resulting therefrom.
Reducing E.sub.m occurs by replacing an abrupt drain doping profile with a more gradually varying doping profile. A more gradual doping profile distributes E.sub.m along a larger lateral distance so that the voltage drop is shared by the channel and the drain. Absent a gradual doping profile, an abrupt junction can exist where almost all of the voltage drop occurs across the lightly-doped channel. The smoother the doping profile, the smaller E.sub.m is.
The simplest method to obtain a gradual doping at the drain-side channel is to use a dopant with a high diffusivity, for example, phosphorus instead of arsenic for an n-channel device. The faster-diffusing phosphorus readily migrates from its implant position in the drain toward the channel creating a gradually doped drain and consequently a smoother voltage profile. Unfortunately, however, the high diffusivity of phosphorus, in addition to creating a gradual lateral doping profile, also increases the lateral and vertical extents of the junction. Enlarging the junctions may bring about harmful short-channel effects and/or parasitic capacitances. Short-channel effects may result in less well-predicted threshold voltage, larger subthreshold currents, and altered IV characteristics.
The most widely-used device structure for achieving a doping gradient at the drain-side of channel is through use of spacers such as spacers 32 and 34. Spacers bring about formation of a lightly-doped drain ("LDD") structure. An LDD structure is made by a two-step implant process. The first step takes place after the formation of the gate. For an n-channel device, a relatively light implant of phosphorus is used to form the lightly doped region adjacent the channel (i.e., the LDD implant). The LDD implants are also referred to as N.sup.- and P.sup.- implants because of their lower concentrations. A conformal CVD oxide film is then deposited over the LDD implant and interposed gate. The oxide is then anisotropically removed, leaving spacers immediately adjacent sidewall surfaces of the gate conductor. After the spacers are formed, a second implant takes place at a higher dosage than the first implant. The second implant is chosen to use the same implant "type" (i.e., n or p) as the first. The higher concentration source/drain implants are also referred to as N.sup.+ and P.sup.+ implants. The source/drain implant is masked from areas adjacent the gate by virtue of the pre-existing spacers. Using an n-type example, the first implant (LDD implant) may use phosphorus, while the second implant (source/drain implant) uses arsenic. The spacers serve to mask the arsenic and to offset it from the gate edges. By introducing spacers after the LDD implant, the LDD structure offers a great deal of flexibility in doping the LDD area relative to the source/drain area. The LDD area is controlled by the lateral spacer dimension and the thermal drive cycle, and is made independent from the source and drain implant (second implant) depth. The conventional LDD process, however, sacrifices some device performance to improve hot-carrier resistance. For example, the LDD process exhibits reduced drive current under comparable gate and source voltages.
A thermal anneal step is required after ion implantation in order to diffuse and activate the implanted ions and repair possible implant damage to the crystal structure. An anneal can occur in a furnace or the more modern rapid-thermal-anneal ("RTA") chamber. An RTA process is typically performed at 420-1150.degree. C. and lasts anywhere from a few seconds to a few minutes. Large area incoherent energy sources were developed to ensure uniform heating of the wafers and to avoid warpage. These sources emit radiant light which allows very rapid and uniform heating and cooling. Wafers are thermally isolated so that radiant (not conductive) heating and cooling is dominant. Various heat sources are utilized, including arc lamps, tungsten-halogen lamps, and resistively-heated slotted graphite sheets. Most heating is performed in inert atmospheres (argon or nitrogen) or vacuum, although oxygen or ammonia for growth of silicon dioxide and silicon nitride may be introduced into the RTA chamber.
The temperature and time required for an RTA are tailored to the implant type and to the implant's purpose. Dopants with a low diffusivity require higher anneal temperatures to activate and position the dopants. Dopants with a high diffusivity require lower anneal temperatures. In addition, a higher concentration of the dopants requires higher anneal temperatures. The dopants used for the LDD implants require lower temperature anneals since any additional migration of these dopants is especially harmful. Any migration towards the channel will contribute to short-channel effects and any vertical migration will increase the parasitic capacitance. In a conventional LDD, the LDD implants are performed first and any subsequent thermal anneal to activate and diffuse the subsequent source/drain implants will also thermally affect the LDD implants. A process would be desirable that could reverse the LDD formation process and enable the performance of the high-temperature thermal anneals first. This would allow a lower temperature anneal for the LDD implant which would not induce excessive migration of the dopants.